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M65665DSP
PICTURE-IN-PICTURE SIGNAL PROCESSING
REJ03F0012-0100Z Rev.2.00 Sep.04.2003
Description
The M65665DSP is a PIP (Picture in Picture) signal processing LSI, whose sub-picture input is composite signal or component signals(Y/C or Y/U/V) for NTSC , PAL-M , PAL-N. The built-in field memory (168k-bit RAM) , V-chip data slicer and analog circuitries lead the high quality PIP system low cost and small size.
Features
* * * * * Internal V-chip data slicer (for sub-picture) Vertical filter for sub-picture (Y signal) Base band com filter (2 Line) Single sub-picture (selectable picture size : 1/9 , 1/16) Sub-picture processing specification (1/9 , 1/16 size) : Quantization bits Y, B-Y, R-Y : 7 bits Horizontal sampling 229 pixels (Y), 57 pixels (B-Y, R-Y) Vertical lines 69/ 52 lines * Frame (sub-picture) on/off * Built-in analog circuits : Two 8-bit A/D converters (for sub-picture signal) Three 8-bit D/A converters (for Y, U and V of sub-picture) Auto Slicer(Sync Sep.), Sync-tip-clamp, VCXO, OSD switch, etc.. 2 * I C BUS control (parallel/serial control) : PIP on/off , Frame on/off (programmable luma level), Sub-picture size (1/9, 1/16), PIP position (free position), Picture freeze , Y delay adjustment, Chroma level, Tint, Black level, Contrast ...etc..
Application
NTSC , PAL-M , PAL-N color TV
Recommended Operating Conditions
Supply voltage range --------------------- 3.2 to 3.5 V Recommended supply voltage --------------------- 3.3 V
Rev.2.00, Sep.04.2003, page 1 of 17
1 2 3 4 5 6 7
M65665DSP
SWM OSD_SEL SDATA SCLK DVdd DVss BGPS
8
Y(R)OUT OSD_RIN AGnd(DAC) U(G)OUT OSD_GIN VZ V(B)OUT OSD_BIN Vdd(DAC) VD HD AVss(VCXO) X'tal(PAL-N) X'tal(PAL-M) X'tal(NTSC) BIAS FILTER AVdd(VCXO)
Rev.2.00, Sep.04.2003, page 2 of 17
SCK
9 10 11 12 13 14 15 16 17 18 19 20 21
Pin Configuration (Top View)
BGPM FSC TEST5 TESTEN SWMG RESET CSYNCS AVdd(ADC) Vin(ADC) Uin(ADC) VRB Yin(ADC) VRT
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
XXXXXX M65665DSP
CVBSIN(ADC) AVss(ADC) CIN(ADC)
42 Pin SDIP Package : 42P4B
M65665DSP
37
Block Diagram
19
21
Sub picture (CVBS or Y(Y/C)) 42 Vertical Filter Y PIP Field Memory U Comb Filter Demod. & TINT V DAC I2C BUS Sub-DAC DAC I2C BUS Sub-DAC I2C BUS Sub-DAC DAC L.P.F. SW A/D
Y/R OUTPUT
24 20
Sub picture (Y(Y/U/V)) Sub picture(U) SW DEMUX & Encoder A/D MUX
Rev.2.00, Sep.04.2003, page 3 of 17 U/G OUTPUT 39 B.P.F. Analog Switch Output Control & RGB Matrix Timing Gen. V/B OUTPUT 36 B.Gate & P.D. Sync. Sep.(digital) 1 Sync. Auto Slice(analog) VCXO Sync. Slice(analog) I2C BUS PIP SW Rextin Gextin Bexttin OSD_SEL 41 38 35 2 I 2C I/F V-CHIP Data Slicer 14 AGND 34 31 40 23 DVDD DGND 5 6 RESET TESTEN 10 12 11 7 8 9 13 + 15 Ext. C-sync 25
Sub picture(V)
Sub picture(C)
18 17 22 33 32
Main VD
Main HD
26
27
28
29
30
4
SCL
3
SDA
AVDD
16
M65665DSP
Absolute Maximum Ratings
(Vss=0 V)
Limits Parameter Supply voltage (3.3V) Input voltage (except for 5V input) Input voltage (5V) Output voltage Output current (*1) Operating temperature Storage temperature Symbol VDD3 VI3 VI5 VO IO Topr Tstg Min. -0.3 -0.3 -0.3 -0.3 IOH=-4 -10 -50 Max. 4.2 VDD3+0.3 5.25 VDD3+0.3 IOL=4 70 125 Unit V V V V mA deg. deg. Conditions
Note : 1. Output current per output terminal. But Pd limits all current.
THERMAL DERATING (MAXIMUM RATING)
POWER DISSIPATION Pd (mW)
2000 1600
1350
1200 800 400 0 0 25 50
750
70
75
100
125
AMBIENT TEMPERATURE Ta (deg.)
Recommended Operating Conditions
(Ta = 25 C, unless otherwise noted)
Parameter Supply voltage Operating frequency "H" Input voltage (CMOS interface) "L" Input voltage (CMOS interface) Output current (output buffer) Output load capacitance Symbol VDD3 fopr VIH VIL IO COL Min. 3.2 VDD3x0.7 0 Typ. 3.3 14.32 Max. 3.5 VDD3 VDD3x0.3 2 20 Unit V MHz V V mA pF Include pin capacitance (7pF) Conditions
Rev.2.00, Sep.04.2003, page 4 of 17
M65665DSP
DC Characteristics
(Ta = 25 deg. unless otherwise noted) (VSS=0V)
Limits Parameter Input voltage (3.3V CMOS interface) Input current (3.3V CMOS interface) Input voltage schmitt (5.0V CMOS interface) L H L H - + Input current (5.0V CMOS interface) CMOS output voltage CMOS output current Output leakage current Input pin capacitance Output pin capacitance Bi-directional pin capacitance Operating current 3.3V supply Hysteresis L H L H L H L H Symbol VIL VIH IIL3 IIH3 VTVT+ VH IIL5 IIH5 VOL VOH IOL IOH IOZL IOZH CI CO CIO IDD Min. 0 2.52 -10 -10 0.8 1.4 0.3 -100 -10 3.25 2 -10 -10 Typ. 7 7 7 140 Max. 0.81 3.6 10 10 1.65 2.7 1.2 10 10 0.05 -2 10 10 15 15 15 Unit V V A A V V V A A V V mA mA A A pF pF pF mA VDD=3.6V,VI=0V VDD=3.6V,VI=3.6V VDD=3.3V,|IO|=1A VDD=3.3V,VOL=0.4V VDD=3.3V,VOL=2.6V VDD=3.6V,VO=0V VDD=3.6V,VO=3.6V f=1MHz,VDD=0V Conditions VDD=2.7V VDD=3.6V VDD=3.6V,VI=0V VDD=3.6V,VI=3.6V VDD=3.3V
Rev.2.00, Sep.04.2003, page 5 of 17
M65665DSP
Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Name SWM OSD_SEL SDATA SCLK DVdd DVss BGPS SCK BGPM FSC TEST5 TESTEN SWMG RESET CSYNCS AVdd(ADC) VIN(ADC) UIN(ADC) VRB YIN(ADC) VRT CIN(ADC) AVss(ADC) CVBSIN(ADC) AVdd(VCXO) FILTER BIAS X'tal(NTSC) X'tal(PAL-M) X'tal(PAL-N) AVss(VCXO) HD VD Vdd(DAC) OSD_BIN V(B)OUT VZ OSD_GIN U(B)OUT AVss(DAC) OSD_RIN Y(R)OUT I/O CMOS output CMOS input CMOS input/output (5V)*1 CMOS input (5V)*1 Digital Vdd Digital Vss CMOS output CMOS input CMOS output CMOS input CMOS input CMOS input CMOS input CMOS input CMOS input Analog Vdd Analog Analog Analog Analog Analog Analog Analog Vss Analog Analog Vdd Analog Analog Analog Analog Analog Analog Vss CMOS input (5V)*1 CMOS input (5V)*1 Analog Vdd Analog Analog Analog Analog Analog Analog Vss Analog Analog Function PIP switch output Output OSD select IIC SDA input/output IIC SCL input VDD for digital part VSS for digital part Test output Test input Test output Test input Test input Test input PIP switch output enable Power on reset input Sub picture external c-sync input Vdd for internal ADC Sub picture V input of ADC Sub picture U input of ADC Low level reference voltage output of ADC Sub picture Y input of ADC High level reference voltage output of ADC Sub picture C input of ADC VSS for internal ADC Sub picture CVBS input of ADC Vdd for VCXO VCXO filter voltage connection VCXO bias voltage connection X'tal of NTSC connection X'tal of PAL-M connection X'tal of PAL-N connection Vss for VCXO Main picture HD input Main picture VD input Vdd for DAC OSD input of B Sub picture V or B output Voltage reference output of DAC OSD input of G Sub picture U or G output Vss for DAC OSD input of R Sub picture Y or R output connect to GND connect to GND connect to GND connect to GND connect to VDD Remarks
Note : 1. (5V) means 5V I/F tolerant
Rev.2.00, Sep.04.2003, page 6 of 17
M65665DSP
Basic Application Example 1
When using any or all of the information contained in this diagrams, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products.
Dig.
Ana.
Digital +3.3V power supply Digital GND Analog +3.3V power supply Analog GND
22 pin input level

Sub C(Y/C) input
0.01u
22 23 24
21 20 19
0.01u 0.1u 0.01u 0.1u 0.1u
pedestal 0.7Vpp(typ)
Sub Y(Y/U/V) input
20 pin input level white peak
Sub CVBS and Y(Y/C) input
24 pin input level white peak 0.66V(max) pedestal sync tip 0.47u 1.0Vpp (max) 0.033u 0.22u 18 p X1
Ana.
M65665DSP
0.1u 3.3 K
25 26 27
0
18 17 16 15 13 12 11 10 9 8 7 6 14
3.3 M
Sub U input Sub V input
0.66V (max)
1.0Vpp (max) pedestal sync tip
Ana.
18 pin input level 0.7Vpp (typ) 10u 10K pedestal 17 pin input level 0.7Vpp (typ) pedestal
28 29 30 31 32 33
X1 : SIWARD 1-781-377-21(14.318180MHz)
32 pin /33 pin input level 3.3V-5.0V 0V 36 pin output level pedestal 0.7Vpp (typ)
+
Dig. Dig.
15 pin input when CSYNC of sub picture is fed from external. 3.3V 0V 2 pin input level 3.3V 0V
Main HD input Main VD input
Ana.
34 35 36 37 38 39 40 41 42
OSD B input
0.1u 0.01u 0.01u 0.1u 0.01u
PIP V(B) output
39 pin output level 0.7Vpp (typ) OSD G input PIP U(G) output 42 pin output level
Dig.
5 4 3 2 1
pedestal
I2C BUS Clock input I2C BUS DATA input /output OSD selection input PIP SW output 1 pin output level
3.3V 0V
white peak 0.7V (typ) back ground pedestal
OSD R input PIP Y(R) output
0.1u 0.01u
Rev.2.00, Sep.04.2003, page 7 of 17
M65665DSP
Basic Application Example 2
When using any or all of the information contained in this diagrams, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products.
Dig.
Ana.
Digital +3.3V power supply Digital GND Analog +3.3V power supply Analog GND
22 pin input level

Sub C(Y/C) input
0.01u
22 23 24 25 26 27
0
21 20 19 18 17 16 15 13 12 11 10 9 8 7 6 14
0.01u 0.1u 0.01u 0.1u 0.1u
Ana.
pedestal 0.7Vpp(typ)
Sub Y(Y/U/V) input
20 pin input level white peak
24 pin input level white peak 0.66V(max) pedestal sync tip 0.47u 1.0Vpp (max) 0.033u 0.22u 18 p 18 p 18 p 32 pin /33 pin input level 3.3V-5.0V 0V 36 pin output level pedestal 0.7Vpp (typ) X1 X2 X3 3.3 K
M65665DSP
Sub CVBS and Y(Y/C) input
Ana.
0.1u
3.3 M
Sub U input Sub V input
0.66V (max)
1.0Vpp (max) pedestal sync tip
18 pin input level 0.7Vpp (typ) 10u 10K
Dig.
28 29 30 31 32 33
0 0
pedestal 17 pin input level 0.7Vpp (typ) pedestal
Main HD input Main VD input
Ana.
34 35 36 37 38 39 40 41 42
15 pin input when CSYNC of sub picture is fed from external. 3.3V 0V 2 pin input level 3.3V 0V
OSD B input
0.1u 0.01u 0.01u 0.1u 0.01u
PIP V(B) output
39 pin output level 0.7Vpp (typ) OSD G input PIP U(G) output 42 pin output level
5 4 3 2 1
pedestal
I2C BUS Clock input I2C BUS DATA input /output OSD selection input PIP SW output 1 pin output level
3.3V 0V
white peak 0.7V (typ) back ground pedestal
OSD R input PIP Y(R) output
0.1u 0.01u
X1 : SIWARD 1-781-377-21(14.318180MHz) X2 : SIWARD 1-795-487-11(14.302444MHz) X3 : SIWARD 1-795-486-11(14.328224MHz)
Rev.2.00, Sep.04.2003, page 8 of 17
+
Dig. Dig.
M65665DSP
TV System Block Diagram
< Y/U/V PIP Mixing system >
Composite Video Signal
Y Y/C Separation C
Y C Video Signal Processing
Y U V Matrix
R G B Deflection Unit Yoke
Y/C Separated Video Signal
Y C Y U V
CV/Y M65665DSP PIP Signal Processing Y U V SWM
HD
VD
Y/U/V Component Video Signal
< R/G/B PIP&OSD Mixing system > Y Y/C Separation C
Composite Video Signal
Y C
R
Video Signal Processing
G B
Y/C Separated Video Signal
Y C
CV/Y
M65665CFP/SP PIP Signal Processing
OSD_R OSD_G OSD_B OSD_F.B.
Y/U/V Component Video Signal
Y U V
R G B SWM
Deflection Unit
HD VD
Yoke
Rev.2.00, Sep.04.2003, page 9 of 17
M65665DSP
I2C Register Information
When using any or all of the information contained in this table, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products.
1/9 Ref. Value Address 00h Bit <7> <6> <5> <4> <3> <2> <1> <0> 01h 02h 03h <7:0> <7:0> <7> <6:0> 04h <7> <6:0> 05h <7> <6> <5:0> 06h <7:6> Symbol DISP SIZE_V SIZE_H WEN BGC BGCS FREE_RUN XTALVLATCH VXA<7:0> HXA<7:0> DECODE CONTRAST<6:0> KILLER U_DAC<6:0> GRC YUVN_RGB_SEL TINT<5:0> EXT_SC_SEL<1:0> Read/ Write W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NTSC 1h 0 0 1h 0 0 0 0 20h 20h 0 32h 0 32h 1h 0 0 1h Trinorma 1h 0 0 1h 0 0 0 1h 20h 20h 0 32h 0 32h 1h 0 0 1h Remarks Sub picture display : [0] off , [1] on Sub picture vertical size : [0] 1/9 , [1] 1/16 Sub picture horizontal size : [0] 1/9 , [1] 1/16 Sub picture : [0] Still , [1] Moving Back ground display : [0] off , [1] on Sub picture mute : [0] off , [1] on VCXO oscilation : [0] Lock , [1] Free run X'tal change V-Latch Enable : [0] disable , [1] enable Sub picture vertical position Sub picture horizontal position Sub picture color decoder reset : [1] reset Sub picture Y or R DAC output amplitude control Sub picture color killer : [0] enable , [1] disable Sub picture U or G DAC output amplitude control Frame display : [0] off , [1] on PIP output mode selection : [0] YUV , [1] RGB Sub picture TINT control Sub picture c-sync sep. selection : [0] int. digital , [1] int. auto slice , [2] ext.(18 pin) , [3] int. analog Sub picture int. c-sync sep. threshhold setting. Sub picture display timing adjust Sub picture input selection : [0] YC , [1] N.A. , [2] CVBS , [3] YUV Sub picture Burst Gate Pulse position setting Main/Sub switch delay control Sub picture Y/C delay adjust Back ground U level setting Sub picture Y bright control V-chip decode mode : [0] off , [1] on Back ground V level setting Back ground Y level setting Sub picture V pedestal level (2's comp) Sub picture U pedestal level (2's comp)
<5:4> <3:0> 07h <7:6> <5:0> 08h 09h 0Ah <7:4> <3:0> <7:5> <4:0> <7> <6:4> <3:0> 0Bh <7:4> <3:0>
DCONT<1:0> HT<3:0> INPUT_SEL<1:0> BG_START<5:0> ADJ<3:0> YDL<3:0> BGBY<2:0> Y_OFFSET<4:0> VCHIP ONLY BGRY<2:0> BGY<3:0> PEDESTV<3:0> PEDESTU<3:0>
W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R
0 0 0 0 0 0 0 0 0 0 0 0 0
0 Ah 2h 0Fh 4h Ah 0 0Fh 1h 0 6h 0 0
0 Ah 2h 0Fh 4h Ah 0 0Fh 1h 0 6h 0 0
Rev.2.00, Sep.04.2003, page 10 of 17
M65665DSP
1/9 Ref. Value Address 0Ch Bit <7> <6> <5:4> Symbol UV_FILTER_OFF SET_ACC SYSTEM_MODE<1:0> Read/ Write W/R W/R W/R Reset Value 0 0 0 NTSC 1h 0 0 Trinorma 1h 1h 3h Remarks Sub picture U,V output filter [0] on , [1] off Address 0Dh,0Eh setting mode : [0] fixed value, [1] released to MCU System : [0]NTSC,[1]PAL-M,[2]PAL-N, [3]N.A. when AUTO_ENABLE=0b [0]NTSC,[1]NTSC/PAL-M,[2]NTSC/PALN,[3]NTSC/PAL-M/PAL-N when AUTO ENABLE=1h Address 11h<6:0>,12h-14h setting mode : [0] fixed value, [1] released to MCU Address 15h-17h setting mode : [0] fixed value, [1] released to MCU Sub picture sync. delay control Sub picture color control parameter when YUV input Sub picture chroma : [0] X1 , [1] X2 Sub picture killer on when burst PLL is unlock : [0] off , [1] on For test : 0 set only Internal chroma comb filter : [0] on , [1] off Sub picture Y clamp time constant : [0] X2 , [1] X1 Sub picture AFC time constant : [0] X2 , [1] X1 Sub picture color decoder amplitude System automatic judgment : [0] off , [1] on PIP V-position mode : [0] VXA , [1] (VXA)X1.2 when VD is 50Hz Main picture PAL-N : [0] enable , [1] disable Invert main picture field definition : [0] normal , [1] invert Invert sub picture field definition : [0] normal , [1] invert Vertical display mode when PAL-N input : [0] normal , [1] wide Main picture field fix : [0] not fix , [1] fix Automatic 50/60Hz Judgment : [0] enable , [1] disable
<3> <2> <1:0> 0Dh <7:4> <3> <2> <1> <0> 0Eh <7> <6> <5:0> 0Fh <7> <6> <5> <4> <3> <2> <1> <0>
SET_SIZE SET_VCHIP SYNC_DELAY<1:0> YUV_COL<3:0> C_GAIN_SEL WDOF_KILLER_ON SET_YUV CVF BITSEL AFCBITSEL ACC_LEVEL<5:0> AUTO_ENABLE V50POSIEN PALN_DISABLE INV_RFF INV_WFF VMODE RFF_FIX AUTO_RFF_FIX
W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 15h 0 0 0 0 0 0 0 1h
0 0 0 0 0 1h 0 0 0 0 15h 1h 0 0 0 0 1h 0 0
Rev.2.00, Sep.04.2003, page 11 of 17
M65665DSP
1/9 Ref. Value Address 10h Bit <7:6> <5:4> <3:0> 11h <7> <6:0> 12h 13h <7:0> <7:2> <1:0> 14h <7:6> <5:0> 15h <7> <6> <5> <4:0> 16h 17h 18h <7:0> <7:0> <7> <6:4> <3:0> 19h <7:5> <4> <3:0> 1Ah 1Bh <7:0> <7:6> <5> <4> <3:0> 1Ch <7> <6:0> 1Dh 1Eh <7:0> <7:0> Symbol NO_BST_LVL<1:0> BW_DET_LVL<1:0> PALRY<3:0> FVJDGSEL HYA<6:0> VYA<7:0> HX<5:0> HP<1:0> MVC<1:0> VXS<5:0> Read/ Write W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NTSC 0 0 0 0 37h 44h 1Eh 0 0 29h 0 0 0 11h 40h 82h 1h 0 Ch 0 0 0 0 0 0 0 0 0 32h E6h 0 Trinorma 0 1h 1h 0 37h 44h 1Eh 0 0 29h 0 0 0 11h 40h 82h 1h 0 Ch 0 0 2h 26h 0 0 0 0 0 32h E6h 0 Remarks For test BW det. threshold setting : [0] off , [1] 16mV , [2] 32mV , [3] 64mV Threshold control of ident judgment of sub picture decoder Vertical frequency judging mode [0]:based on 5 field, [1]:based on 4 field. Sub picture horizontal display pixel Sub picture vertical display line number Sub picture horizontal capture position (coarse) Sub picture horizontal capture position (fine) Sub picture c-sync input mask period : [0] 48usec , [1] 44usec , [2] 53usec , [3] off Sub picture sample start line For test : 0 set only For test : 0 set only For test : 0 set only Data slicer line selection Data slicer start bit detection parameter Data slicer data slice parameter Frame data independent control : [0] disable , [1] enable Frame data independent B-Y data setting Frame data independent Y data setting Frame data independent R-Y data setting Sub picture Y output HPF : [0] on , [1] off Frequency adjustment control when free run mode (2's comp) Parameter setting for PAL-M/NTSC judgment Ext. port (7 pin) : [0] "0" output , [1] "1" output , [2 or 3] Sub BGP Invert U,V output value : [0] normal , [1] invert Sub picture AFC : [0] on , [1] off Parameter setting for PAL-M/NTSC judgment For test Sub picture V or B DAC output amplitude control For test For test
PLUS
LINE_NUM<4:0> STB_DLY<7:0> L_LEVEL<7:0> EDGE_ON BGBY_EDGE<2:0> BGY_EDGE<3:0> BGRY_EDGE<2:0> HPFOFF FREE_RUN_ADJ<3:0> SUB_PALM_JUDGE <7:0> EXPORT<1:0> INV_UV AFC_OFF HADJ<3:0> PINOE V_DAC<6:0> PINOE<7:0>
Rev.2.00, Sep.04.2003, page 12 of 17
M65665DSP
1/9 Ref. Value Address 1Fh Bit <7:6> <5> <4> <3> <2> <1> <0> 20h <7> <6> <5> <4> <3> <2> <1> <0> 21h 22h 23h 24h <7:0> <7:0> <7:0> <7:0> Symbol SYSTEM_STATE<1:0> MAIN_PALN SUB_UNLOCK SUB_PALN RDOF SUB_BW WDOF KILLERSTATUS Read/ Write R R R R R R R R R R R R R R R R R R R Reset Value NTSC Trinorma Remarks Color state : [0] NTSC , [1] PAL-M , [2] PAL-N , [3] N.A. (Read only) Main is : [0] not PAL-N , [1] PAL-N (Read only) VCXO is : [0] Lock , [1] Unlock (Read only) Sub is : [0] not PAL-N , [1] PAL-N (Read only) Main picture V sync is [0] present , [1] not present (Read only) Sub picture burst is : [0] not present , [1] present (Read only) Sub picture V sync is [0] present , [1] not present (Read only) Sub picture killer status : [0] not active , [1] active (Read only) Test use (Read only) Sub picture V sync is [0] present , [1] not present (Read only) EDS data flag of even field : [0] no EDS , [1] EDS (Read only) EDS data flag of odd field : [0] no EDS , [1] EDS (Read only) Test use (Read only) Read request of even field : [0] no , [1] requesting (Read only) Read request of odd field : [0] no , [1] requesting (Read only) Even field Sliced data upper 8bit (Read only) Even field Sliced data lower 8bit (Read only) Odd field Sliced data upper 8bit (Read only) Odd field Sliced data lower 8bit (Read only)
WDOF EDS_ACK2 EDS_ACK1 SIGNAL_OK READ_REQB READ_REQA PDB<15:8> PDB<7:0> PDA<15:8> PDA<7:0>
Rev.2.00, Sep.04.2003, page 13 of 17
M65665DSP The relation of input signal 32-pin (Main-HD) and 33-pin (Main-VD) is shown below
prohibition time of changing 33-pin signal
0
32-pin input
(Main-HD)
33-pin input
-10usec +10sec +21.75sec +53.5sec +41.75sec
(Main-VD) [Even to Odd]
33-pin input
(Main-VD) [Odd to Even]
20s
20s
20s
20s
20s
20s
VD input 4H 1H end of vertical equalization pulse
20s 31.75s
20s
20s
20s
20s
20s
VD input
Driving Method and Operating Specification for Serial Interface Data (1) Serial data transmission completion and start A low-to-high transition of the DATA (serial data) line while the CLK (serial clock) is high, that completes the serial transmission and makes the bus free. A high-to-low transition of the DATA line while the CLK is high, that starts the serial transmission and waits for the following CLK and DATA inputs. (2) Serial data transmission The data are transmitted in the most significant bit (MSB) first by one-byte unit on the DATA line successively. Onebyte data transmission is completed by 9 clock cycles, the former 8 cycles are for address/data and the latter one is for acknowledge detection. (In writing state, SDATA outputs `L' under these two conditions ; 1) the coincidence of two address data for the address data transmission, 2) the completion of 8-bit setting data transfer. In reading state, SDATA outputs `L' with the address coincidence and SDATA becomes high-impedance for detecting acknowledge input from the master (micro processor) after sending 8-bit setting data.) For address/data transmission, DATA must change while CLK is 'L'. (The data change while CLK is 'H' or the simultaneous change of CLK and DATA, that will be a false operation because of undistinguished condition from the completion / start of serial data transfer). After the beginning of serial data transmission, the total number of data bytes that can be transferred are not limited. (3) The byte format of data transmission (The sequence of data transmission) a. The byte format during data writing to M65665DSP are shown as follows. In right after the forming of serial data transmitting state, the slave address 24h (00100100b) is transferred. Afterwards, the internal register address (1 byte) and writing data (by 1 byte unit) are transferred successively. Several bytes of
Rev.2.00, Sep.04.2003, page 14 of 17
M65665DSP writing data can be handled in the one transmission. In this operation, the setting data are written into the address register whose address is increased one in initially transferred internal register address. b. The byte format during data reading from M65665DSP are shown as follows. Before data reading from M65665DSP, whose internal address need to be set by the data reading/transmitting. After the data reading/transmitting, the operation of "serial data transmission completion and start" (described in (1)) is necessary. Continuously, the slave address 25h (00100101b) is sent, and then the read out data are available on SDATA as `L'/`high-impedance' pattern. Several bytes of reading data can be handled in the one transmission, too. In this operation, the setting data also are written into the address register whose address is increased one in initially transferred internal register address.
The examples of serial byte transmission format
(1) The writing operation of the setting data (AAh) into M65665DSP internal address of 00h
Transmission Activation
Confirmation of bus free (DATA='H')
S
24h
A
00h
A
AAh
AE
S : Operation of serial transmission start A : Acknowledge detection E : Operation of serial transmission completion
(2) The writing operation of the setting data (FFh, 80h, EEh) into M65665DSP internal address of 04h to 06h
Transmission Activation
Confirmation of bus free (DATA='H')
S
24h
A
04h
A
FFh
A
80h
A
EEh
AE
(3) The reading operation of the setting data from M65665DSP internal address of 00h
Transmission Activation
Confirmation of bus free (DATA='H')
S
24h
A
00h
AES
25h
A
$$h
A'
A' : Bus free operation by the master (micro processor)
Rev.2.00, Sep.04.2003, page 15 of 17
M65665DSP (4) The reading operation of the setting data from M65665DSP internal address of 04h to 06h.
Confirmation of bus free (DATA='H')
Transmission Activation
S
24h
A
04h
AES
25h
A
$$h A" $$h A"
$$h
A'
A" : Output 'L' operation by the master (micro processor)
Timing Diagram
1 2 3 4 5 6 7 8 9 1
SCLK (4 pin)
SDATA (3 pin)
Bit7 (MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 (LSB)
ACK Detec.
Bit7 (MSB)
SDATA (3 pin) (Read data)
Bit7 (MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 (LSB)
Bit7 (MSB)
Rev.2.00, Sep.04.2003, page 16 of 17
M65665DSP
42P4B
JEDEC Code -- Weight(g) 4.1 Lead Material Alloy 42/Cu Alloy
MMP
Plastic 42pin 600mil SDIP
EIAJ Package Code SDIP42-P-600-1.78
c
Package Dimensions
E
1
21
Symbol
D
L
A
e
b1
b
b2
A1
A2
SEATING PLANE
A A1 A2 b b1 b2 c D E e e1 L
Dimension in Millimeters Min Nom Max -- -- 5.5 0.51 -- -- -- 3.8 -- 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 -- 1.778 -- -- 15.24 -- 3.0 -- -- 0 -- 15
e1
Rev.2.00, Sep.04.2003, page 17 of 17
42 22
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